Espressif Systems /ESP32-P4 /H264_DMA /OUT_INT_CLR_CH0

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Interpret as OUT_INT_CLR_CH0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OUT_DONE_CH0_INT_CLR)OUT_DONE_CH0_INT_CLR 0 (OUT_EOF_CH0_INT_CLR)OUT_EOF_CH0_INT_CLR 0 (OUT_DSCR_ERR_CH0_INT_CLR)OUT_DSCR_ERR_CH0_INT_CLR 0 (OUT_TOTAL_EOF_CH0_INT_CLR)OUT_TOTAL_EOF_CH0_INT_CLR 0 (OUTFIFO_OVF_L1_CH0_INT_CLR)OUTFIFO_OVF_L1_CH0_INT_CLR 0 (OUTFIFO_UDF_L1_CH0_INT_CLR)OUTFIFO_UDF_L1_CH0_INT_CLR 0 (OUTFIFO_OVF_L2_CH0_INT_CLR)OUTFIFO_OVF_L2_CH0_INT_CLR 0 (OUTFIFO_UDF_L2_CH0_INT_CLR)OUTFIFO_UDF_L2_CH0_INT_CLR 0 (OUT_DSCR_TASK_OVF_CH0_INT_CLR)OUT_DSCR_TASK_OVF_CH0_INT_CLR

Description

TX CH0 interrupt clr register

Fields

OUT_DONE_CH0_INT_CLR

Set this bit to clear the OUT_DONE_CH_INT interrupt.

OUT_EOF_CH0_INT_CLR

Set this bit to clear the OUT_EOF_CH_INT interrupt.

OUT_DSCR_ERR_CH0_INT_CLR

Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.

OUT_TOTAL_EOF_CH0_INT_CLR

Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.

OUTFIFO_OVF_L1_CH0_INT_CLR

Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.

OUTFIFO_UDF_L1_CH0_INT_CLR

Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.

OUTFIFO_OVF_L2_CH0_INT_CLR

Set this bit to clear the OUTFIFO_OVF_L2_CH_INT interrupt.

OUTFIFO_UDF_L2_CH0_INT_CLR

Set this bit to clear the OUTFIFO_UDF_L2_CH_INT interrupt.

OUT_DSCR_TASK_OVF_CH0_INT_CLR

Set this bit to clear the OUT_DSCR_TASK_OVF_CH_INT interrupt.

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